Using UVM for verification of most common RTLs
Writing Verilog test benches is always fun after completing RTL Design. You can assure clients that the design will be bug-free in tested scenarios. As System complexity is growing day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability helping verification engineers quickly locate hidden bugs. The System Verilog lags structured approach whereas UVM works very hard on forming a general skeleton. The addition of the configuration database Shifts the way we used to work with the Verification Language in the past. Within a few years, verification engineers recognize the capabilities of UVM and adopted UVM as a defacto standard for the RTL Design verification. The UVM will have a long run in the verification domain hence learning of UVM will help VLSI aspirants to pursue a career in this domain.
What you’ll learn
- Verification of Combinational Circuits.
- Verification of Sequential Circuits.
- Verification of Common Bus Protocols viz. APB, AXI.
- Verification of Communication Protocols viz. UART, SPI, I2C.
- Understanding usage of Virtual Sequencer, Sequence Library and TLM analysis FIFO.
Course Content
- Agenda –> 1 lecture • 2min.
- Verification of Combinational Circuit : 4-bit Multiplier –> 5 lectures • 24min.
- Verification of Sequential Circuit : Data Flipflop –> 5 lectures • 28min.
- Verification of UART –> 16 lectures • 1hr 34min.
- Verification of SPI Memory –> 12 lectures • 1hr 19min.
- Verification of I2C Memory –> 8 lectures • 34min.
- Veriicantion of APB_RAM –> 8 lectures • 1hr.
- Verification of AXI Memory –> 18 lectures • 2hr 10min.
- Understanding usage of Sequence Library –> 3 lectures • 17min.
- Understanding TLM Analysis FIFO –> 9 lectures • 29min.
- Understanding Virtual Sequencer –> 8 lectures • 26min.
Requirements
Writing Verilog test benches is always fun after completing RTL Design. You can assure clients that the design will be bug-free in tested scenarios. As System complexity is growing day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability helping verification engineers quickly locate hidden bugs. The System Verilog lags structured approach whereas UVM works very hard on forming a general skeleton. The addition of the configuration database Shifts the way we used to work with the Verification Language in the past. Within a few years, verification engineers recognize the capabilities of UVM and adopted UVM as a defacto standard for the RTL Design verification. The UVM will have a long run in the verification domain hence learning of UVM will help VLSI aspirants to pursue a career in this domain.
This is a Lab-based course designed such that anyone with the fundamentals of UVM could understand how verification engineers use UVM to perform verification of commonly used RTLs and sub-blocks in FPGA. The course covers verification of the combinational circuit like combinational adder, Sequential circuit like Data flip-flop, communication interfaces like a clock generator, UART, SPI, and I2C, and Bus protocols like APB, AXI, and demonstration of few useful UVM concepts like a virtual sequencer, TLM analysis FIFO, and a sequence library.